This specification defines the number of pins available for user defined signaling interfacing between the carrier card and the IO mezzanine module. By using the programmable flexibility of FPGA I/O, it is expected that the user defined pins can support both differential and single ended signaling. This enables the reuse of pins for different I/O standards and aids in minimizing the size of the physical connector required. The intent of this specification is to define the number of user defined pins supported by both the high-pin and low pin-count connectors.