EMERGING biomedical and wireless applications would
benefit from the availability of digital processors with
substantially improved energy-efficiency. One approach to realize
ultra-low energy processors is to scale the supply voltage
aggressively to below the transistor threshold [1], yet the
major increase in delay variability under process, voltage, and
temperature (PVT) variations combined with the dominance of
leakage power makes robust sub-threshold computations and
further voltage scaling extremely challenging.